1. Field of the Invention
The present invention relates to a serial-to-parallel conversion apparatus, a semiconductor device, an electronic device, and a data transmission system, and more particularly to an apparatus for transmitting digital image information from an information processing apparatus to a device such as a liquid crystal display, a large-size high-resolution flat panel display, a liquid crystal projector, or a multi-display system.
2. Description of Related Art
A data transmission system for transmitting image information such as that shown in FIG. 16 is known in the art. In such a system, it is known to use one or more pairs of wires as transmission means for transmitting digital image information to a display device. This technique is called LVDS (low voltage differential signal) transmission.
In the data transmission system shown in FIG. 16, data is transmitted from one information processing apparatus 500 to another information processing apparatus 600 via an LVDS cable.
In a transmitting apparatus, parallel data 513 such as image information output from the information processing apparatus 500 at the transmitting end is converted into serial data 514 by a parallel-to-serial converter 520 in accordance with a clock signal CL 511 produced by a PLL 530 by way of multiplying the frequency of a dot clock signal CL 510.
The resultant serial data 514 is transmitted together with a clock signal CL 512 similar to the dot clock signal CL 510 via drivers 540 (540-1, 540-2, . . . ), a cable 560, and receivers 630 (630-1, 630-2, . . . ).
In accordance with a clock signal CL 602 generated by a PLL 620 by way of multiplying the frequency of a clock signal CL 601 similar to the clock signal CL 512, a serial-to-parallel converter 610 converts the serial data 604 to parallel data 605 and supplies the resultant parallel data 605 to the information processing apparatus 600.
In the case where the cable comprising one or more pairs of wires, the dot clock signal CL 510 (512, 601, 603) and the coded serial data 514 (604) are transmitted, while in the receiving apparatus the clock signal CL 602 is generated by multiplying the frequency of the dot clock signal CL 601 and the serial data is reconverted to parallel data in accordance with the obtained clock signal CL 602.
When serial data is converted to parallel data, it is required to detect boundaries (start positions of respective data strings) between two adjacent data strings of the serial data. As can be seen from FIG. 18, information used to detect the boundaries is given by the clock signal CL 601 (CL 510, CL 512). Because one cycle of the clock signal CL 601 corresponds to the length of one unit data string, the timing of each rising edge (or falling edge) of the clock signal CL 601 has a particular relation with the start position of a data string of the serial data 604. Therefore, the start position of each data string of the serial data 604 can be detected by detecting a rising edge (or falling edge) of the clock signal CL 601, and thus it is possible to convert serial data to parallel data without producing a bit position error.
However, the dot clock signal CL 510 output from the information processing apparatus 500 often has large jitter which affects extraction of the clock signal or multiplication of the dot clock signal performed in the receiving apparatus and thus causes a failure in conversion to parallel data or in reproduction of data.
That is, as shown in FIGS. 16 and 18, when parallel data (A0), . . . , (Ak) are input to the parallel-to-serial converter 520 via parallel data input terminals Txin0-Txink, the parallel-to-serial converter 520 sequentially samples the parallel data (A0), . . . , (Ak) from data to data in synchronization with the clock signal CL 511 generated by means of frequency multiplication thereby converting them into serial data (A0 . . . Ak).
The resultant serial data (A0 . . . Ak) is output together with the dot clock signal CL510 from the driver 540 and transmitted via the LVDS cable 560.
The serial data (A0 . . . Ak) 604 is then input, as shown in FIGS. 16 and 18, to the serial-to-parallel converter 610 via the serial data input terminal Rxin and sampled in synchronization with the clock signal CL602 generated by way of frequency multiplication.
As described above, because the start position of the serial data (A0 . . . Ak) can be detected from the timing of a rising edge (or falling edge) of the clock signal CL601, it is possible to output the parallel data (A0), . . . , (Ak) so that A0 corresponds to Rxout0 and A1 corresponds to Rxout1.
If jitter occurs in the clock signal CL510, a phase difference occurs between the clock signal CL511 multiplied in the transmitting apparatus and the clock signal CL602 multiplied in the receiving apparatus, as shown in FIG. 19, and thus the serial-to-parallel converter 610 cannot perform a correct conversion upon the parallel data converted into serial form by the parallel-to-serial converter 520. The term xe2x80x9cjitterxe2x80x9d is generally used to describe a waveform disturbance such as that shown in FIG. 19.
More specifically, referring to the timing chart of FIG. 17 illustrating the relationship among the serial data 604, the parallel data 605, and CL602 (multiplied signal) in the serial-to-parallel converter 610, jitter causes a deviation between the timing of the clock signal CL601 or 602 and the start position of the nth data string of the serial data. Such a deviation can cause incorrect detection of a boundary between adjacent data strings (the start position of a data string) of the serial data.
The major cause of the above problem is in that the serial-to-parallel converter 610 performs the converting operation in synchronization with the clock signal CL602 multiplied by the PLL 620.
In the parallel-to-serial converter 520, the clock signal 511 is generated by the PLL 520 by way of frequency multiplication, while in the serial-to-parallel converter 610 the clock signal 602 is generated by the PLL 620 by way of frequency multiplication. Therefore, if the clock signal 510 includes jitter, a timing deviation between the clock signals 511 and 602 occurs as shown in FIG. 19. When there is such jitter, if the serial data 604 generated on the basis of the multiplied clock signal 511 is sampled in synchronization with the clock signal 602, the resultant parallel data may be incorrect.
The phase error generated by the jitter can cause an incorrect detection of a signal level. For example, a signal level which should be determined as a low level may be incorrectly determined as a high level. As a result, it becomes difficult or even impossible to correctly read the content of data. That is, because the serial-to-parallel conversion is performed on the basis of the out-of-synchronization clock signal, data may be incorrectly converted into parallel form. For example, data which should be converted to R0, G0, and B0 may be incorrectly converted to G0, B0, and R1.
Furthermore, in order that a VCO (voltage controlled oscillator) of the PLL can operate in a stable fashion, it is required that the voltage of a power supply should be stable enough. However, in general, fluctuations of the voltage of the power supply occur owing to noise in a logic circuit or the like, and thus the operation of the PLL become unstable. For the above reasons, use of two PLLs, one in the transmitting apparatus and the other in the receiving apparatus, results in a reduction in a margin for correct reception of data. Furthermore, in order that each PLL operates in a stable fashion, it is required that the power supply voltage should be stabilized over the entire apparatus. This results in an increase in cost.
In view of the above problems, it is an object of the present invention to provide a serial-to-parallel conversion apparatus, a semiconductor device, an electronic device, and a data transmission system, in which serial data is correctly converted to parallel data without encountering a conversion timing error in a serial-to-parallel converter thereby making it possible to correctly display an image at a receiving end.
The present invention provides:
(1) A serial-to-parallel conversion apparatus comprising: data conversion means (data computer) for sampling a first data string in the form of serial data, which includes one or more unit data strings each including a predetermined number of bits and which is input after a synchronization period, in accordance with a clock signal which has been used to generate the serial data by converting original parallel data into serial form, thereby converting the serial data to parallel data from one unit data string to another; and signal generation means (signal generator) for generating a synchronization signal corresponding to the synchronization period, on the basis of the serial data, wherein: the serial data includes a second data string for synchronization detection within the synchronization period, the second data string including one or more unit data strings each having a predetermined bit pattern; the signal generation means generates the synchronization signal when detecting the unit data string in the second data string; and the data conversion means detects the start position of the unit data string in the first data string on the basis of the synchronization signal.
In the apparatus according to (1), serial data is converted by the data conversion means to parallel data. The sampling clock signal used herein to perform the conversion of the serial data into the parallel data is the same sampling clock signal as that used in conversion from original parallel data to that serial data. Therefore, even if the clock signal used in the parallel-to-serial conversion includes jitter, no timing error occurs in the serial-to-parallel-conversion because the same clock signal is used. Furthermore, in the present invention, instead of generating a sampling clock signal on the basis of a reference clock signal (such as a dot clock signal), the synchronization signal is generated by the signal generation means by detecting the second data string in the serial data. On the basis of this synchronization signal, the position of a unit data string which appears first in the first data string is detected thereby determining the start timing of outputting the parallel data.
The present invention also provides serial-to-parallel conversion apparatus described below in (2) to (8).
(2) A serial-to-parallel conversion apparatus according to (1), wherein the bit pattern of the unit data string in the second data string is a unique pattern different from any bit pattern that unit data strings in the first data string can have.
In the apparatus according to (2), it is possible to prevent a unit data string in the first data string from being detected incorrectly as a data string in the second data string.
(3) A serial-to-parallel conversion apparatus according to (2), wherein the signal generation means (data storage device) includes data string detection means, to which the clock signal and the serial data are input, for detecting the unit data string in the second data string from the serial data thereby outputting the synchronization signal.
In the apparatus according to (3), it becomes possible to output a synchronization signal each time a unit data string in the second data string is detected from the serial data. Because the unit data string in the second data string is generated periodically, the synchronization signal is output each time the unit data string is generated.
(4) A serial-to-parallel conversion apparatus according to (3), wherein the data string detection means (data storage device) includes: data holding means for temporarily holding the serial data from one unit data string to another in accordance with the clock signal; and synchronization signal outputting means (synchronization signal outputting device) for outputting the synchronization signal when the unit data string held by the data holding means has the predetermined bit pattern.
In the apparatus according to (4), each unit data string is temporarily held by the data holding means, and the synchronization signal is output when the unit data string held by the data holding means has the same pattern as the predetermined pattern set in advance in the synchronization signal outputting means. This ensures that the second data string can be detected in a highly reliable fashion.
(5) A serial-to-parallel conversion apparatus according to (1), wherein the signal generation means includes: data string detection means, to which the clock signal and said serial data are input, for outputting an auxiliary synchronization signal each time a unit data string in the second data string is detected from the serial data; and synchronization signal outputting means for outputting the synchronization signal when detecting a plurality of auxiliary synchronization signals output from the data string detection means.
In the apparatus according to (5), it is possible to generate an auxiliary synchronization signal each time a unit data string in the second data string is detected from the serial data. Because the unit data string in the second data string is generated periodically, the synchronization signal is output each time the unit data string is generated. This makes it possible to prevent an incorrect detection of the start point of the first data string when a single auxiliary synchronization signal is generated erroneously.
(6) A serial-to-parallel conversion apparatus according to (5), wherein the data string detection means includes: data holding means for temporarily holding the serial data from one unit data string to another in accordance with the clock signal; and auxiliary synchronization signal outputting means (auxiliary synchronization signal outputting device) for outputting the auxiliary synchronization signal when the unit data string held by the data holding means has the predetermined bit pattern.
In the apparatus according to (6), each unit data string is temporarily held by the data holding means, and the auxiliary synchronization signal is output if the unit data string held by the data holding means has the same pattern as the predetermined pattern set in advance in the auxiliary synchronization signal outputting means. This ensures that the second data string can be detected in a highly reliable fashion.
(7) A serial-to-parallel conversion apparatus according to (5) or (6), wherein the signal generation means further includes period control signal generation means (prior control signal generator) for generating a period control signal whose voltage level is set to a predetermined value over a second period entirely containing a first period, from its beginning to its end, in which a plurality of auxiliary synchronization signals are successively output, and wherein the auxiliary synchronization outputting means outputs the auxiliary synchronization signal when the unit data string has the predetermined bit pattern.
In the apparatus according to (7), any auxiliary synchronization signal appears during the second period substantially corresponding to the synchronization period. Therefore, unlike the apparatus according to (4), incorrect detection of the synchronization signal does not occur even if the bit pattern of unit data strings in the second data string is not unique.
(8) A serial-to-parallel conversion apparatus according to (7), wherein the detection signal generation means (first setting device) includes: first setting means for setting the start timing of the second period in accordance with the auxiliary synchronization signal and the clock signal; second setting means (second setting device) for setting the end timing of the second period in accordance with the auxiliary synchronization signal and the clock signal; and means for controlling the voltage of the period control signal in accordance with the setting of the first and second setting means.
In the apparatus according to (8), the first setting means and second setting means set the start timing and end timing, respectively, of the second period by counting the clock signal generated after the auxiliary synchronization signal is output, thereby generating the period control signal.
The present invention also provides a semiconductor device including a serial-to-parallel conversion apparatus according to one of (1) to (8), wherein the serial-to-parallel conversion apparatus is disposed on a semiconductor substrate.
The semiconductor device may be formed in the form of a single chip on which the serial-to-parallel conversion apparatus is formed, and may be installed in various types of information processing apparatus.
The present invention also provides an electronic device including: a serial-to-parallel conversion apparatus according to one of (1) to (8); and a display unit for displaying an image in accordance with parallel data converted by the serial-to-parallel conversion apparatus.
In this electronic device, because the serial-to-parallel conversion apparatus based on one of (1) to (8) is employed, an image can be displayed on the displaying unit without encountering degradation in image quality which may otherwise occur during data transmission.
The present invention also provides a data transmission system for transferring data from a transmitting apparatus to a receiving apparatus, the transmitting apparatus comprising: an information supplying source for outputting a first clock signal and parallel data; means (second clock signal generator) for generating a second clock signal by multiplying the first clock signal; and parallel-to-serial conversion means (parallel-to-serial conversion apparatus) for sampling the parallel data in synchronization with the second clock signal and serially outputting data strings comprising unit data strings each having a period corresponding to one cycle of the first clock signal such that a second data string including one or more unit data strings each having a particular bit pattern for synchronization detection is serially output during a synchronization period and such that a first data string including one or more unit data strings is serially output during a period following the synchronization period, the receiving apparatus comprising: means for receiving the serial data (receiving device) and the second clock signal from the parallel-to-serial conversion means; signal generation means for detecting the second data string in the serial data and generating a synchronization signal corresponding to the synchronization period; serial-to-parallel conversion means (serial-to-parallel conversion apparatus) for detecting the start position of the unit data string contained in the first data string in the serial data on the basis of the synchronization signal and sampling the serial data in synchronization with the second clock signal thereby converting the serial data into parallel data from one unit data string to another.
In this data transmission system, the serial-to-parallel conversion apparatus according to (1) is disposed as the receiving apparatus. Thus, the receiving apparatus in this system also has similar advantages to those achieved by (1).
In this data transmission system, the transmitting apparatus preferably includes electric-to-optical signal conversion means (electric-to-optical signal converter) for converting the serial data in the form of an electric signal to an optical signal, wherein the electric-to-optical signal conversion means is preferably formed of a surface emitting laser.
Conventionally, semiconductor lasers of the edge emitting type are widely used in communication systems and other applications. However, edge emitting lasers have a relatively large threshold current in the range from 20 to 50 mA, and thus a large bias current is required. Another problem of edge emitting lasers is that the threshold current greatly depends on temperature, and thus it is required to control the current by way of feedback control (auto power control) while monitoring the optical output so that the optical output is maintained constant. Therefore, a special type of driver is required to use an edge emitting laser. This results in an increase in complexity of the system. In contrast, the surface emitting laser employed in the preferable mode of the system has a small threshold current in the range from 0.05 mA to 10 mA, and the temperature dependence of the threshold current can be suppressed to an extremely low level. Therefore, the surface emitting laser can be driven using a simple modulation circuit. In the simplest case which needs the lowest cost, an optical signal corresponding to an electric signal can be generated by simply connecting the surface emitting laser to the parallel-to-serial conversion apparatus.
Furthermore, because the surface emitting laser operates in the single longitudinal mode, it has high monochromaticity and high stability in terms of wavelength which allow it to be coupled with an optical fiber with a high coupling efficiency. Another advantage of the surface emitting laser is that because it emits light in a direction perpendicular to the semiconductor substrate surface, the surface emitting laser can be mounted by means of chip bonding on an integrated circuit chip such as a CMOS circuit into the form of a hybrid integrated circuit. This form needs a single package and thus a reduction in cost can be achieved. Furthermore, optical signal transmission can be performed at a high transmission rate which allows an increase in processing speed.
Furthermore, in the above data transmission system, the electric-to-optical conversion means is preferably a multi-wavelength surface emitting laser.
In this preferable mode, it is possible to dispose light emitting parts which emit light with different wavelengths at small intervals of the order of 10 xcexcm. Therefore, light rays with various wavelengths emitted from the multi-wavelength surface emitting laser can be coupled into at least single optical transmission means with a relatively large diameter. This allows serial data and a multiplied clock signal or a plurality of serial data and a multiplied clock signal to be transmitted using the single optical transmission means.
Furthermore, in the above data transmission system, it is desirable that a transmission medium for transmitting the clock signal and the serial data be formed of a plurality of optical fibers, and the electric-to-optical signal conversion means be formed of a multi-beam surface emitting laser.
In this preferable mode, the multi-beam surface emitting laser includes the plurality of light emitting parts which are arranged in a one-dimensional or two-dimensional fashion on a semiconductor substrate chip, the light incidence ends of the plurality of optical fibers can be easily positioned with respect to the array of light emitting parts thereby coupling the multi-beam surface emitting laser with the plurality of optical fibers. This makes it possible to achieve transmission via a plurality of optical fiber at low cost.